1. Field of the Invention
The present invention relates to a level shift circuit used as an interface between circuits operating on different power source voltages and a switching power source apparatus employing the level shift circuit.
2. Description of the Related Art
A switching power source apparatus used for a flat panel display, which is strongly required to be thinner, is frequently of a half-bridge type with two switching elements and a current resonant type capable of reducing a switching loss. To miniaturize and thin the flat panel displays such as LCD TVs and other consumer appliances, switching power source apparatuses used with them are required to operate at higher frequencies with the use of smaller parts.
The half-bridge switching power source apparatus employs two n-type MOSFETs and a level shift circuit to transfer a low-side control signal to a high side. When the switching power source apparatus is used with a consumer appliance, an input voltage to a primary-side converter of the apparatus comes from a PFC (power factor correction) circuit conforming to high-frequency regulations and is generally about DC 420 V. Accordingly, the level shift circuit of the switching power source apparatus must shift a low-side voltage to about 420 V. In connection with this, various problems arise and measures to deal with the problems must be taken.
FIG. 1 is a view illustrating a half-bridge, current-resonant power source apparatus employing a level shift circuit according to a related art. The level shift circuit serves as a high-side driver in a control circuit 2.
In FIG. 1, the control circuit 2 alternately turns on/off high- and low-side switching elements to control frequencies and change the charge/discharge period of a resonant capacitor Ci, thereby controlling power induced on the secondary side of a transformer.
Japanese Unexamined Patent Application Publication No. H09-200017 (Patent Document 1) discloses a semiconductor apparatus that prevents a malfunction of a flip-flop that may occur due to a dv/dt current caused by a transient voltage dv/dt, thereby protecting switching elements. FIG. 2 is a circuit diagram illustrating the semiconductor apparatus described in the Patent Document 1. This apparatus includes a level shift circuit serving as a high-side driver HD1. In FIG. 2, switching elements 17 and 18 are connected in series between a power source and the ground, to form a half-bridge power device 19. The switching elements 17 and 18 are, for example, IGBTs (insulated gate bipolar transistors). A connection point N1 of the switching elements 17 and 18 is connected to a load 21 that is an inductive load such as a motor.
The high-side switching element 17 carries out a switching operation between a reference voltage that is a voltage at the connection point N1 and a power source voltage (for example, 420 V) supplied from the power source. On the other hand, the low-side switching element 18 carries out a switching operation between a reference voltage that is a ground voltage and the voltage at the connection point N1.
In the high-side driver HD1 illustrated in FIG. 2, a transient voltage dv/dt is applied, depending on a switching state of the half-bridge power device 19, to a line L1 extending from the connection point N1 to anodes of diodes 8 and 9 and to a high-side circuit that operates on a reference voltage that is a voltage on the line L1. MOSFETs 20 and 30 each have a high withstand voltage (usually about 700 to 1100 V) with respect to drains thereof, and for this, each MOSFET has a large element region and parasitic capacitance among the drain, source, back gate, gate, and sub-substrate thereof.
Accordingly, if there is no filter circuit 26, the high-side driver HD1 passes a dv/dt current that is caused by the product of a transient voltage dv/dt and the parasitic capacitance between the drain and source of each of the MOSFETs 20 and 30. At this time, resistors 4 and 5 simultaneously cause voltage drops to operate inverters 6 and 7 and erroneously apply high-level signals to set and reset terminals of a flip-flop 12.
To prevent this, the high-side driver HD1 illustrated in FIG. 2 arranges the filter circuit 26 before the flip-flop 12. Even if the transient voltage dv/dt is applied to the line L1 to simultaneously pass the dv/dt current to the MOSFETs 20 and 30 and simultaneously cause voltage drops at the resistors 4 and 5, the filter circuit 26 blocks the high-level signals from the inverters 6 and 7.
Namely, the filter circuit 26 provides no high-level signals to the flip-flop 12 until a delay time determined by a time constant of a CR filter of the filter circuit 26 elapses. This delay time is set to be longer than the duration of the transient voltage dv/dt, so that no high-level signal due to the dv/dt current is passed to the flip-flop 12, thereby preventing the flip-flop 12 from malfunctioning.
At this time, the pulse width of each of ON and OFF signals provided by a pulse generator 10 is set to be sufficiently longer than the duration of the transient voltage dv/dt, i.e., the delay time of the filter circuit 26, so that output signals from the inverters 6 and 7 based on the ON and OFF signals from the pulse generator 10 are given to the flip-flop 12 to normally operate the flip-flop 12.
FIG. 3 is a timing chart illustrating operation of the semiconductor apparatus of FIG. 2 according to the related art of the Patent Document 1. To turn on the switching element 17, the pulse generator 10 provides a high-level ON signal and a low-level OFF signal. The ON-side CR filter receives a high-level signal from the inverter 7 and provides an output signal that gradually rises until a capacitor 25 is charged. Thereafter, the output signal similarly falls. When the output from the ON-side CR filter completely rises, the flip-flop 12 outputs a high-level signal from an output terminal Q thereof.
To turn off the switching element 17, the pulse generator 10 outputs a low-level ON signal and a high-level OFF signal. In this case, the OFF-side CR filter receives a high-level signal from the inverter 6 and provides an output signal that gradually rises until a capacitor 24 is charged. Thereafter, the output signal similarly falls. When the output from the OFF-side CR filter completely rises, the flip-flop 12 outputs a low-level signal from the output terminal Q.
The switching element 17 is ON during a period in which the flip-flop 12 outputs a high-level signal from the output terminal Q. Compared with the case having no filter circuit 26, the output from the output terminal Q of the flip-flop 12 is delayed by the delay time of the ON-side (OFF-side) CR filter.
As mentioned above, the pulse width of an ON (OFF) signal to the MOSFET 20 (30) must be longer than the delay time provided by the filter circuit 26. To prevent malfunctions, the delay time (filtering time) of the filter circuit 26 must be long. This, however, increases power consumption. To deal with this problem, the Patent Document 1 also discloses a semiconductor apparatus having a protection circuit made of a logic circuit that produces no delay time.
Japanese Unexamined Patent Application Publication No. H04-230117 (Patent Document 2) discloses a level shift circuit having an interference eliminating function with respect to the transient voltage dv/dt. This level shift circuit has a pulse filter circuit that identifies, based on a pulse width, a pulse caused by the transient voltage dv/dt and passes only a normal operation pulse, thereby preventing a malfunction due to the transient voltage dv/dt.
Japanese Unexamined Patent Application Publication No. H08-65143 (Patent Document 3) discloses a level shift circuit having a reset priority circuit. The reset priority circuit operates a reset level circuit with an input signal whose value is lower than that of an input signal for operating a set level circuit, to thereby turn off a power MOSFET. This level shift circuit enlarges a reset voltage drop resistor, or adjusts the input threshold values of devices to read the reset and set voltage drop resistors, thereby realizing the reset priority and preventing malfunctions due to noise.
The reset priority concept is applicable to the level shift circuit illustrated in FIG. 2. By enlarging the reset-side resistor 4, the level shift circuit of FIG. 2 can realize the reset priority to turn off the high-side switching element 17, thereby preventing the switching elements 17 and 18 from simultaneously turning on.
Japanese Unexamined Patent Application Publication No. H09-172366 (Patent Document 4) discloses an inverter apparatus that interposes a transmission unit between an ON-side pulse transmission system and an OFF-side pulse transmission system, to lower the resistance value of one of the transmission systems when the other transmits a signal. In addition, this inverter apparatus enlarges a resistance value on a reset side, to realize a reset priority configuration. When a transient voltage dv/dt occurs, the OFF-side pulse transmission system causes a large resistance voltage drop. At this time, the interposed transmission unit lowers the resistance value of the ON-side pulse transmission system, thereby preventing a resistance voltage drop from occurring on the ON side. As a result, an OFF-side pulse voltage is transmitted to a flip-flop, to reset the flip-flop and prevent a malfunction due to the transient voltage dv/dt.